1. Field of the Invention
Embodiment of the present invention relate generally to the field of memory devices and more particularly, to systems and methods of wear leveling for memory devices.
2. Description of the Related Art
Computer systems and other electrical systems generally include one or more memory devices. For example, computers often employ NOR flash memory and NAND flash memory. NOR and NAND flash each have certain advantages over the other. For example, NOR flash memory typically has slower write and erase speeds than NAND flash. Further, NAND flash memory typically has more endurance than NOR flash memory. However, NOR flash memory typically enables random access to data stored within the memory devices, whereas, NAND flash memory generally requires accessing and writing data in larger groups. For example, NAND flash memory typically includes a plurality of blocks that each includes a plurality of pages, wherein each page includes a large number of bytes of data. In operation, data is erased one block at a time, and written one page at a time.
Advances in memory technologies have given rise to increased silicon area reduction, while achieving increased storage capacity. Unfortunately, this exponential shrinking of the on-silicon structures has created heavy interference, impacting memory cell cycling endurance. Over time, an aggregation of data operations (e.g., read/write operations) may degrade a memory cell. For example, NAND memory cells have a limited number of write/erase cycles (e.g. 100,000 program/erase cycles).
To prolong the life of these memory devices, “wear leveling” can be applied to spread data across various physical sectors of the memory. Wear leveling generally includes writing data to the various sectors to ensure an even use of the cells to prevent certain portions of the memory array from prematurely failing. Wear leveling may include initially writing the data to one of the various sectors in the memory array, or may include moving the data from one physical sector within the memory array and writing that same data to another physical sectors in the memory array.
Some memory technologies (e.g., page flash memories) feature an additional level of granularity inside each sector called sub-sectors. Sub-sectors are segments of memory inside the sector of a memory. The sub-sectors may be individually accessed (e.g., programmed and/or erased). Accordingly, the sub-sectors have separate cycling, and thus, different wear-out from other sub-sectors within the memory. Unfortunately, traditional wear leveling techniques have not effectively accounted for sub-sector wear, especially in high data cycling application (e.g., page-flash implementations), where the number of cycles may reach into the hundreds of thousands.